In recent years, integration of LSI has become more intensive, and the element sizes are being vastly reduced. In a lithography process directly related to element microfabrication, a photoresist is formed on a processing layer (semiconductor layer or a metal layer), and the photoresist is exposed via a mask followed by development, so that the photomask pattern is transferred onto the photoresist. The layer is then subjected to microfabrication through etching using as an etching mask the photoresist on which the pattern is transferred, before finally the photoresist is removed. In a recent lithography process for element microfabrication, the exposure wavelength is greater than the size of transfer pattern (photomask), and therefore there is a problem of faultiness of the pattern transfer linearity (accordance of the pattern before transfer and the pattern after transfer). This is called an optical proximity effect. The optical proximity effect is a phenomenon in which the 90° corner (corner section) rounds and the line end on the pattern transfer decreases due to diffraction of light caused by the exposure wavelength greater than the transfer pattern. Further, similarly, the optical proximity effect appears as a phenomenon in which the line width, which is supposed to be the same, varies depending on the density.
The optical proximity effect is, as it is obvious, mainly caused by a proximity effect of light; however, it is also affected by the resist process (pre-exposure bake, post-exposure bake (PEB), development) or by the underlayer (shape, structure, material etc. of the underlayer). The optical proximity effect may make the product circuit pattern to fall outside the spec (design size).
To prevent unwanted effects of optical proximity effect upon the exposure (may be called “photo”, hereinafter), a mask used for exposure is generally subjected to a correction process in advance so that the predicted shifting (displacement) amount due to optical proximity effect is modified. This correction is called optical proximity effect correction (may be referred to as “OPC” hereinafter).
In recent years, a phenomenon called etching shift, which occurs in the OPC due to proximity effect of pattern in the etching process after exposure, has become a problem. Unlike the optical proximity effect, in the proximity effect in the etching process, the reaction of the circuit material to the etching changes depending on the space to the proximal pattern or the pattern density in the neighborhood. To accurately analyze the reaction, it is necessary to analyze radical reaction of etching including the shape of the neighborhood portion. A recent general practical method of finding the etching shift is not calculation of an accurate reaction formula, but a fitting calculation using an empiric formula (or a rule) on the basis of the space to the proximal pattern or the pattern density in the neighborhood. A correction of the etching proximity effect based on this fitting calculation (or a rule) is called an etching proximity effect correction (Etching-PC, hereinafter). The Process Proximity Effect Correction; (may be referred to as “PPC” hereinafter) including a proximity effect correction (Etching-PC) to the etching shift is now considered more important.
With the recent complication of process technologies, the circuit pattern set by the designer and the mask pattern used in the exposure process greatly differs. This prevents easy estimation of the shape of the resist pattern formed on a wafer based on the mask pattern. Therefore, it is necessary to check whether the mask pattern is appropriate (whether the mask pattern is capable of forming the desired circuit pattern) using a simulator (of lithography or etching).
For example, Patent Document 1 (Japanese Unexamined Patent Publication Tokukai 2005-121943) discloses a method of extracting the difference between (i) anticipated value pattern data generated through estimation of the photomask pattern at the time of exposure transfer onto a wafer and modification of the CAD pattern data, and (ii) the pattern data resulted from the simulation denoting a result of light intensity simulation to the CAD pattern data, and determines whether the difference is not more than a predetermined allowable value. In this way, the reasonability of the pattern image on a wafer is examined. Note that, the OPC data examination tool using this technology has been commercially available via some EDA (Electronic Design Automation) vendors.
Further, a non-patent Document 1 (J. Kim, L. Wang, et al. “Model-Based Full-chip Validation for 65 nm Lithography Process Development”, SPIE BACUS Symposium, Yokohama, Vol. 5853-42, pp. 599-606, 2005/April) discloses a method of examining the reasonability of the pattern image on a wafer through estimation of the shape of photomask pattern at the time of transfer onto a wafer through lithography simulation, extracting the difference between the target CAD pattern data and the simulation result, and determining whether the difference is not more than a predetermined allowable value. The OPC data examination tool using this technology has been commercially available via some EDA vendors. The non-patent Document 2 (A. Sezginer, F. X. Zach, et al. “Process-window-aware-RET and OPC”, SPIE Symposium, San Jose, Vol. 6156, No. 615613, recently completed volumes, 2006) is a specific example of PPC of this technology.
With reference to FIG. 4(a) and FIG. 4(b), the following explains a concrete example of a method of examining the reasonability of the OPC photomask (the photomask created by OPC) for forming a circuit pattern of a memory cell (SRAM), i.e., for examining whether the mask pattern is capable of forming a desired circuit pattern, by way of lithography simulation. First, the exposure pattern on a wafer is found by lithography simulation based on the OPC photomask pattern data of FIG. 4(a). FIG. 4(a) shows the exposure pattern on the wafer as a simulation result. Next, the distance between the edges of the exposure pattern on the wafer is checked and the two edges (in this example, see the part indicated by the broken line of FIG. 4(a)) with a distance (about 110 nm) significantly smaller than the designed value (170 nm) is determined as a part of short-circuit. The OPC photomask is modified to increase the distance between the edges determined as a part of short-circuit of the exposure pattern on the wafer to 166 nm. As a result, the distance between the edges determined as a part of short-circuit of the OPC photomask is increased from 110 nm to 118 nm. FIG. 4(b) shows an exposure pattern on the wafer (shown as a simulation result in the figure) found by the lithography simulation based on the modified OPC photomask, and the data thereof.
Examples of the method of producing photomask patterns using the OPC are disclosed in many Patent Documents, such as the Patent Document 2 (Japanese Unexamined Patent Publication Tokukai 2005-134520.
The method disclosed in Patent Document 2 first carries out proximity effect correction with respect to the design pattern data (photomask pattern data), and then extracts a part where the process margin decreases using the light intensity simulation (light intensity calculation under best focus, optimal exposure state, out of focus, improper exposure amount). In this way, the pattern is corrected to keep the margin of the part where the extract process margin decreases.
On the other hand, the Patent Document 3 (Japanese Unexamined Patent Publication Tokukai 2005-181636 prepares a desired pattern and a mask pattern corresponding to the desired pattern, and carries out proximity effect correction with respect to the mask pattern, and then sets evaluation points to the edges of the desired pattern, and calculates position errors from the evaluation points and the amount of statistics of the position errors for plural combinations of the process parameters in the variable range of process parameter value previously set. In this way, the mask pattern is corrected according to the amount of statistics.
In recent years, examples of typical production method for photomask pattern data using the OPC (or PPC) include a method of estimating the shift amount of proximity effect using a calculation formula or simulation, and a method of creating a process model for estimating a transfer pattern of the mask pattern in a predetermined process including exposure using the design data of the mask pattern as the input data. Further, in a method of producing photomask pattern data using OPC (or PPC), a designed test pattern is formed on the test mask, and the design data of the test pattern rearranged according to measurement result of length of the test pattern on the test mask is fitted to a result of length measurement of the test pattern on the test mask (Patent Document 4: Japanese Unexamined Patent Publication Tokukai 2004-157160). Since the fitting accuracy becomes higher in this fitting (experimental) model than the conventional theoretical model, the fitting (experimental) model is the main stream of the existing commercially-available tool (provided by EDA vendor).
Examples of recent PPC are disclosed in Patent Documents 3 and 4, Patent Document 5 (Japanese Unexamined Patent Publication Tokukai 2005-99765) and Patent Document 6 (Japanese Unexamined Patent Publication Tokukai 2003-57801).
The Patent Document 4 relates to a method of finding an estimation model of proximity effect of a highly-accurate process, such as a method of finding an unknown parameter using the test pattern made of the repetitive pattern group and the predetermined repetitive pattern group such as a memory cell. Further, the Patent Document 5 relates to a method of effectively carrying out measurement of SEM length and pattern correction by linking the steps (in parallel) by a computer. This method accurately finds addition correction amount (difference) to the optical proximity effect correction. With these methods, it is possible to greatly reduce huge work, burden and time for the conventional (correction) simulation in consideration of calculated many unknown parameters regarding mask reproduction, re-evaluation on the wafer, etching condition etc.
Note that, in LSI designing, application of restriction of critical pattern to the design rule to improve production reliability and process yield is broadly called a DFM (Design for Manufacturability). The necessity of the DFM tends to increase with the recent development of micro-sized (90 nm, 65 nm) LSI (non-patent Document 3: “DFM: beginning of entire revision of semiconductor cost” Nikkei Micro Device Magazine, Nikkei B P, May 2005, p. 25 to 41 (published on May 1, 2005, Page 36)).
The following explains problems of typical conventional technologies.
The biggest problem of the production and validation method of photomask pattern data using a general conventional PPC model is extraction and validation of PPC model. For the recent complication of LSIs as a result of the development of micro LSI elements, a demand of micro-size processing of circuit pattern has come to the front. However, decrease in exposure wavelength of an exposure device is becoming more difficult, and therefore increase in resolution by the decrease in exposure wavelength is not practical. The insufficient resolution has been solved by the super-resolution technology, an (immersion) exposure device, or mask design, but such methods have finally come to the limit in these years. Even with the circuit pattern according to the design rule, it is not so rare that the products include a pattern (critical pattern with a insufficient process margin) causing line-breakage or short-circuit when subjecting the target wiring pattern (layout pattern before modification) to a PPC process to create a photomask and carrying out exposure, development, and etching using the photomask.
FIG. 25 shows a flow of typical conventional PPC process (non-patent Document 2 etc.). As shown in FIG. 25, in the typical conventional PPC process, the mask data is created through etching correction and OPC process with respect to the design data of the circuit pattern. Next, the simulation validation is performed with respect to the mask data. If a problem such as line-breakage is found as a result of the simulation validation, the design data of the circuit pattern is modified, and the etching correction and OPC process is carried out again, or the mask data is corrected. The etching correction is performed with an Etching-PC model or an Etching-PC rule extracted in advance by using the model/rule extraction TEG pattern. Further, the OPC process is performed with an OPC model or an OPC rule extracted in advance by using the model/rule extraction TEG pattern.
FIGS. 26 to 30 show examples of model/rule extraction TEG pattern used for extraction of OPC model, OPC rule, Etching-PC model or Etching-PC rule in the typical conventional PPC process. Another example of mask pattern correction flow is a method of detecting a part where the process margin is reduced by simulation or the like after the PPC process, and then correcting the part, as disclosed in the Patent Document 2 (Japanese Unexamined Patent Publication Tokukai 2005-134520), in the Patent Document 3 (Japanese Unexamined Patent Publication Tokukai 2005-181636), or in the Patent Document 6 (Japanese Unexamined Patent Publication Tokukai 2003-57801).
The inventors of the present invention studied a circuit pattern (photomask pattern before correction) of a metal wire layer (hereinafter referred to as a “MR layer”) of Cu or Al constituting a 130 nm flash memory (hereinafter referred to as a “flash”) and found out that the specific pattern among the circuit pattern (layout pattern before correction) serves as a critical pattern (hereinafter referred to as “line-breakage risk pattern”) which may cause line-breakage when subjecting the pattern to a simulation-based PPC process to create photomask and carrying out exposure, development, and etching using the photomask of said pattern. FIG. 3(a) to FIG. 3(e) show five concrete examples of line-breakage risk pattern in a MR layer of a 130 nm Flash. Note that, the MR layer is a wire layer (hereinafter referred to as “L/S layer” as appropriate) with a line and space circuit pattern.
The line-breakage risk pattern shown in FIG. 3(a) is a H-type crosslinking pattern at least constituted of a first rectangular section, and two first polygon sections (rectangular sections in this example) between which the first rectangular section is caught. The two first polygon sections are in contact with the respective two short-length sides of the first rectangular section. The two ends of the respective sides of the first polygon section in contact with the short-length sides of the first rectangular section each extend outward the short-length sides of the first rectangular section. The length l1 and the width w1 of the first rectangular section satisfy the following conditions.l1<280 nm−2×ES(l1j)w1<240 nm−2×ES(w1j)
In the foregoing conditions, ES(l1j) and ES(w1j) respectively indicate estimated etching shift amounts (amount of size variation due to the etching shift) of the length l1 and width w1 of the first rectangular section of the H-type crosslinking pattern. In this case, the values of ES(l1j) and ES(w1j) are found by back calculation (calculation of finding the length l1 and width w1 of the H-type crosslinking pattern which becomes critical in the etching based on the measurement result of the length l1 and width w1 of the H-type crosslinking pattern which are measured after etching). The etching shift amount depends on the etching process, particularly on the distance to the proximal pattern and the pattern density in the neighborhood. The values l1j and w1j are etching shift variables dependent on the space to the proximal pattern and the pattern density in the neighborhood. The ES(l1j) and ES(w1j) can be found by a rule based on variables l1j and w1j dependent on the space to the proximal pattern and the pattern density in the neighborhood. The rule is determined based on a pattern size of circuit material after the etching using an evaluation mask including the critical pattern. The pattern size of circuit material after the etching using an evaluation mask is specifically found by exposing/developing a resist using an evaluation mask, etching the circuit material using the resist, and measuring the pattern size of the circuit material after the etching. If the rule is applied, the ES(l1j) and ES(w1j) are several discontinuous constituents. Functions or models may be applied instead of the rule. FIG. 31 and FIG. 32 show concrete examples of the etching shift amount. FIG. 31 shows variation in etching shift amount depending on the space to the proximal pattern in a 130 nm process GP layer. The following shows an example of calculation formula (two-dimensional L/S pattern) of etching shift ES in the case of FIG. 31.ES=C0+C1×Space−2+C2×Space−1+C3×Log(Space)
where C0, C1, C2 and C3 are constant values depending on the etching process. FIG. 32 shows an etching shift amount (residual error) dependent on the space of the L/S pattern (line-width after lithography). This is an example of a simple L/S pattern, but it is necessary to consider a long proximal pattern up to 3 or more μ meter in the etching correction, unlike the optical proximity correction (in which a proximal pattern of about 1 to 2 μm is considered).
The line-breakage risk pattern shown in FIG. 3(b) is an opened rectangular pattern at least constituted of a third rectangular section and two third polygon sections (rectangular sections in this example) between which the third rectangular section is caught. One side of the two third polygon sections are in contact with the respective two short-length sides of the third rectangular section. One end of the respective sides of the third polygon sections in contact with the short-length sides of the third rectangular section each extend outward the short-length sides of the third rectangular section. The ends extend outward are opposed without having the third rectangular section inbetween. The length l4 and the width w4 of the third rectangular section satisfy the following conditions.l4<280 nm−2×ES(l4j)w4<240 nm−2×ES(w4j)
In the foregoing conditions, ES(l4j) and ES(w4j) respectively indicate estimated etching shift amounts (amount of size variation due to the etching shift) of the length l4 and width w4 of the third rectangular section of the opened-rectangular crosslinking pattern. In this case, as with the values of ES(l1j) and ES(w1j), the values of ES(l4j) and ES(w4j) are found by back calculation (calculation of finding the length l4 and width w4 of the opened-rectangular crosslinking pattern which becomes a critical pattern by etching, based on the measurement result of the length l4 and width w4 of the opened-rectangular crosslinking pattern measured after etching). The etching shift amount depends on the etching process, particularly on the distance to the proximal pattern and the pattern density in the neighborhood. FIG. 31 and FIG. 32 show concrete examples of the etching shift amount.
The line-breakage risk pattern shown in FIG. 3(c) is a crank-type crosslinking pattern at least constituted of a second rectangular section and two second polygon sections (rectangular sections in this example) between which the second rectangular section is caught. One side of the two second polygon sections are in contact with the respective two short-length sides of the second rectangular section. One end of the respective sides of the second polygon sections in contact with the short-length sides of the second rectangular section each extend outward the short-length sides of the second rectangular section, to be opposite to each other with respect to the second rectangular section. The length l2 and the width w2 of the second rectangular section satisfy the following conditions.l2<280 nm−ES(l2j)w2<240 nm−2×ES(w2j)
In the foregoing conditions, ES(l2j) and ES(w2j) respectively indicate estimated etching shift amounts (amount of size variation due to the etching shift) of the length l2 and width w2 of the second rectangular section of the crank-type crosslinking pattern as with the above case. In this case, as with the values of ES(l1j) and ES(w1j), the values of ES(l2j) and ES(w2j) are found by back calculation (calculation of finding the length l2 and width w2 of the crank-type crosslinking pattern which becomes a critical pattern by etching, based on the measurement result of the length l2 and width w2 of the crank-type crosslinking pattern measured after etching).
The line-breakage risk pattern shown in FIG. 3(d) is a crank-type crosslinking pattern at least constituted of a second rectangular section, two second polygon sections (rectangular sections in this example) between which the second rectangular section is caught and another section. One side of the two second polygon sections are in contact with the respective two short-length sides of the second rectangular section. One end of the respective sides of the second polygon sections in contact with the short-length sides of the second rectangular section each extend outward the short-length sides of the second rectangular section, to be opposite to each other with respect to the second rectangular section. The length l5 and the width w5 of the second rectangular section satisfy the following conditions.l5<280 nm−2×ES(l5j)w5<240 nm−2×ES(w5j)
In the foregoing conditions, ES(l5j) and ES(w5j) respectively indicate estimated etching shift amounts (amount of size variation due to the etching shift) of the length l5 and width w5 of the second rectangular section of the crank-type crosslinking pattern as with the above case. In this case, as with the values of ES(l1j) and ES(w1j), the values of ES(l5j) and ES(w5j) are found by back calculation (calculation of finding the length l5 and width w5 of the crank-type crosslinking pattern which becomes a critical pattern by etching, based on the measurement result of the length l5 and width w5 of the crank-type crosslinking pattern measured after etching).
The line-breakage risk pattern shown in FIG. 3(e) is a projection pattern at least constituted of a rectangular projection section and a polygon main body in contact with one of the short-length sides of the projection section. Two ends of the side of the polygon main body in contact with the short-length side of the projection section each extend outward the short-length side of the projection section. The length l3 and the width w3 of the third rectangular section satisfy the following conditions.l3<280 nm−ES(l3j)w3<240 nm−2×ES(w3j)
In the foregoing conditions, ES(l3j) ES(w3j) respectively indicate estimated etching shift amounts (amount of size variation due to the etching shift) of the length l3 and width w3 of the projection pattern, as with the above case. As with the values of ES(l1j) and ES(w1j), the values of ES(l3j) and ES(w3j) are found by back calculation.
Generation of such critical patterns is caused by improper PPC processes of the conventional PPC model due to development of micro LSIs. This circumstance has raised necessity of modification of extraction of PPC model or an approach (help) from the designer.
However, those critical patterns cannot be detected by a check process based on the conventional light intensity simulation (with varied defocus values and exposure amounts). FIG. 5 and FIG. 6 show concrete examples.
FIG. 5 shows results of photo evaluation of photomasks including critical patterns, performed by the inventors of the present invention. These photomasks are used for a practical process, and has been modified by OPC correction. More specifically, FIG. 5 shows images (upper SEM photo) of the upper surfaces of positive type photoresist patterns captured by a scanning electron microscope (SEM). Each of the positive type photoresists has been subjected to exposure and development on a wafer using the photomask under an exposure amount=33.5 mJ/cm2 and a defocus value=+0.15 μm. The narrow portion of the upper SEM photo is a portion with a risk of line-breakage. The photo evaluation determines, according to a SEM photo such as the one shown in FIG. 5, a positive type photoresist without a top (resist top) in the narrow portion (there is a risk of line-breakage in the etching process) as “NG”, and determines a positive type photoresist with a top in the narrow portion (there is no risk of line-breakage in the etching process) as “GOOD”. The target photomargin in this process (target exposure margin and focus margin) is a range in which the exposure margin (the width of exposure amount ensuring a good result of photo evaluation) is not less than ±3.3%, and the focus margin (the width of defocus value ensuring a good result of photo evaluation) is not less than ±0.18 μm. However, all patterns of photomask in FIG. 5 are evaluated as “NG”. Generation of a positive type photoresist without a top in the narrow portion, which causes a risk of line-breakage in the etching process, is induced by depression in the narrow portion of the positive type photoresist. This derives from light leakage in the narrow portion due to its light intensity contrast less than the other parts.
FIG. 6 shows a light intensity simulation result of a mask including a critical pattern having been modified by OPC correction, corresponding to the positive resist pattern of FIG. 5. As shown in FIG. 6, the light intensity simulation result shows that the width of the narrow portion (width of the resist bottom (bottom section)) is 165 nm, that means there is no risk of line-breakage. Thus, in the mask pattern check by light intensity simulation, risk of line-breakage is not concerned in the etching process, and therefore the narrow portion is not detected as a critical pattern. Therefore, the mask pattern check only by the light intensity simulation causes a possibility of line-breakage at the stage of production of a trial circuit pattern model through exposure, development and etching by using the actual mask created according to the mask pattern. When the occurrence of line-breakage is found, a new mask pattern needs to be produced. This increases development cost and development period.
Further, with the development of micro-sized LSI, high accuracy of PPC model has become a large demand. In the conventional PPC model, a simulation model is created based on a light intensity calculation result obtained by lithography simulation with a limited threshold (variable threshold or fixed threshold) for avoiding short-circuit of simulation pattern and a limited threshold (variable threshold or fixed threshold) for avoiding line-breakage, and the various sizes (line width etc.) of the circuit pattern obtained by exposure, development, and etching of a resist using the mask are calculated according to the simulation model (variable threshold model or fixed threshold model). Further, in a conventional PPC model, a simulation model is created based on a light intensity calculation result obtained by lithography simulation, with a simplified estimation of effect of photoresist development and etching effect. Therefore, to obtain a highly accurate PPC model, the estimation of photoresist shape by way of exposure calculation and development calculation can be performed with higher accuracy. However, the process time of pattern correction increases, and a load of device performing pattern correction calculation increases.
Further, in the case of creating mask pattern data from the design data of a semiconductor circuit, complex data processes such as PPC or auxiliary pattern production are required because of recent development of micro semiconductor. Therefore, after the data processes, a pattern validation (check) process is required to assess adequacy of data results. There are various pattern validation methods. For example, the validation method after PPC may be performed by a method of checking the pattern data after PPC according to the PPC rule, or a method using an empirical model of checking the pattern resulted from exposure whether the pattern satisfies the target size. The pattern validation is becoming more important with the further development of micro semiconductor element. This has caused a demand for a validation technology with high accuracy.
The following explains the problems of Patent Documents of 2, 3, 5 and 6 which are the features to be addressed by the example embodiment presented herein.
FIG. 2 shows a flow chart of a mask pattern data creation process according to the Patent Document 2 (Japanese Unexamined Patent Publication Tokukai 2005-134520).
In the mask pattern data creation process of the Patent Document 2, the design pattern is modified first to satisfy the process margin (S111), and then is modified into a proximity effect correction pattern for realizing the design pattern modified in S111 (S112). Next, the process margin is examined to check whether it is not less than the reference value (S113). Then, any part with process margin out of the reference value is subjected to pattern correction (S114). After output of mask data, a mask is created (S115).
FIG. 1, FIG. 3, and Paragraphs [0017], [0019], [0021], and [0023] of the Patent Document 2 describe conversion of design data into a desired pattern ensuring a desired process margin in S111 before the optical proximity effect correction by changing the pattern of amount delta corresponding to the pattern width L and the pattern gap S, based on the conversion table (table of rules) of FIG. 3. Specifically, the paragraph [0021] of Patent Document 2 reads “the conversion amount delta . . . for maintaining a process margin can be determined by an exposure test using masks of varied parameters of a line width or a space width of the Lines & Space pattern, or by light intensity simulation”.
More specifically, the Patent Document 2 describes that a correction rule for maintaining a process margin is determined by an exposure test using masks of varied parameters of a line width or a space width of the Lines & Space pattern, and the correction is carried out according to the correction rule before and after the optical proximity effect correction.
However, the method of Patent Document 2 carries out correction so as to maintain the process margin of the pattern after the optical proximity effect correction, that is, the method is not to detect and correct a pattern which becomes a critical pattern in the optical proximity effect correction. Therefore, in the method of the Patent Document 2, the area of a local margin degradation point of the design pattern in the optical proximity effect correction cannot be removed before the optical proximity effect correction. This is written in Paragraph [0025] of the Patent Document 2 as “At the stage after the proximity effect correction section S12, a local margin degradation point remains”. Further, in the Patent Document 2, only a mask including Lines & Space pattern is disclosed as a mask for the exposure test, and there is no teaching of a mask including a pattern which becomes critical in the optical proximity effect correction, such as a H-type crosslinking pattern.
Further, paragraph [0024] of the Patent Document 2 reads “the desired pattern may be formed on a portion where the process margin decreases in a two-dimensional manner. For example, . . . in the case where the design pattern 105 is constituted of large-area rectangle and narrow-line patterns, the width 102 of the large-area pattern is a narrow line”. However, a method of detecting a pattern which becomes critical in the optical proximity effect correction before performing the optical proximity effect correction is not found in this description.
Further, Paragraphs [0026] to [0029], and [0035] of the Patent Document 2 disclose pattern correction with respect to an extracted pattern whose process margin is equal to or less than the reference value after the optical proximity effect correction.
However, in the Patent Document 2, the extraction of the part (pattern) whose process margin is equal to or less than the reference value after the optical proximity effect correction is performed by comparison with the distribution form of light intensity obtained by a light intensity simulation. As described above, the conventional check process based on the light intensity simulation is not capable of detecting a pattern which becomes critical in the optical proximity effect correction (shown in FIG. 5 and FIG. 6). Therefore, detection and correction of a pattern which becomes critical in the optical proximity effect correction (shown in FIG. 5 and FIG. 6) is not possible even by a method of pattern extraction and pattern correction after the optical proximity effect correction disclosed in the Patent Document 2.
In conclusion, the OPC process in Patent Document 2 is inadequate, as it is not capable of detecting and correcting a pattern (FIG. 5 and FIG. 6) which becomes critical in the optical proximity effect correction. Therefore, if a lithography process is performed with a photomask which is formed based on the photomask pattern of the Patent Document 2 having been through the OPC process, the process spec (such as process margin) is not achieved in the entire area. Consequently, it becomes necessary to check whether the process spec is satisfied, and correct the layout as required after the photolithography process by way of photo evaluation (evaluation based on an image captured by an electron microscope). That is, it is necessary to correct the design data of photomask after the photolithography process, create a new photomask, and subjects the new mask to photo evaluation again. This brings a great waste of cost and a great delay of development. In view of this problem, there is a demand for a validation technology capable of detecting the critical pattern such as the ones shown in FIG. 5 and FIG. 6, so as to realize a highly-accurate OPC process with which the layout correction after the photolithography process is not necessary.
The Patent Documents 3, 5, and 6 describe existing OPC process flow or PPC process flow. For example, in Patent Document 3, the difference between the target pattern and the estimation (simulation) value is found using the mask pattern data after the OPC process, and the difference is used as an index of mask pattern correction. In Patent Document 5, an unknown parameter is found using a mask including a test pattern. Various test patterns produced from a base pattern or a repetitive pattern with varied biases and pitches are used. In Patent Document 6, the measured length by a SEM and a mask pattern coordinate are associated to find the difference of them, and the difference is used as an index of mask pattern correction. However, these methods carry out validation, extraction, and correction to resulting mask pattern data, that is, carry out validation, extraction, and correction of mask pattern data after creation of mask pattern data. Those methods thus do not allow mask pattern data correction before creation of mask pattern.